With the development of technologies in the semiconductor integrated circuit industry, more and more semiconductor devices can be integrated in one semiconductor integrated circuit (IC), and the size of individual semiconductor devices becomes smaller and smaller. A field-effect transistor (FET) is a typical semiconductor device that constitutes a basic unit of a semiconductor IC. An FET includes a gate structure formed over a semiconductor substrate, as well as a source and a drain formed in the semiconductor substrate and close to the gate structure. Conventionally, the source and drain are formed by doping the semiconductor substrate. With the increasing of the integration level of IC's and the scaling down of the FETs in the IC's, different processes have been developed for forming the source and drain.
One of these processes involves using an epitaxial technique to form the source and drain. According to this process, the semiconductor substrate is etched to form recesses, also referred to as “S/D recesses,” and then a semiconductor material is deposited in the recesses to form the source and drain. In some FETs, the semiconductor material is also deposited above the S/D recesses, and the resulting sources or drains are also referred to as raised sources or raised drains having an elevated portion above the surface of the substrate. The recesses can be hexagonal-shaped recesses, also referred to as sigma-shaped recesses. The process of forming the hexagonal-shaped recesses can include a dry etching to form U-shaped recesses and then a wet etching to form the hexagonal-shaped recesses.
The semiconductor material deposited in the recesses can be different for different types of FETs. For example, for a P-channel FET formed in a silicon (Si) substrate, silicon-germanium (SiGe) can be deposited in the recesses to form the source and drain. Since SiGe has a larger lattice constant than Si, an SiGe source/drain introduces a compressive stress in the channel of the FET, which increases the hole mobility in the channel. Further, for an N-channel FET formed in an Si substrate, phosphorous-doped Si (Si:P) can be deposited in the recesses to form the source and drain.
FIG. 1 schematically shows a conventional semiconductor device 100 including a substrate 102, two gate structures 104 formed over the substrate 102, a hexagonal-shaped S/D recess 106 formed in the substrate 102 and between the gate structures 104 according to conventional technology, and a raised source/drain 108 formed in and over the S/D recess 106 and between the gate structures 104. Each of the gate structures 104 includes a gate dielectric layer 104-2 formed over the substrate 102, a gate electrode 104-4 formed over the gate dielectric layer 104-2, a cap layer 104-6 formed over the gate electrode 104-4, and a spacer 104-8 formed on the side surface of the gate structure, i.e., the side surfaces of the gate dielectric layer 104-2, the gate electrode 104-4, and the cap layer 104-6.
The source/drain 108 includes a buried portion 108-2 formed in the S/D recess 106 and an elevated portion 108-4 formed over the S/D recess 106, i.e., above the top surface of the substrate 102. In the semiconductor device 100, the distance between the elevated portion 108-4 and the gate electrode 104-4, also referred to herein as an “S2G distance,” is determined by the thickness of the spacer 104-8.
The inventors have observed that the conventional semiconductor device 100 has structural and operational deficiencies.